我自己写了个VHDL文件，要实现某种功能，我想知道如何自定义个元件，让它具有我的文件中描述的功能？

你所说的自定义元件是不是指的把你自己写的VHDL文件转换成符号可以在图形输入法中用？如果是 这样的话，先把这个VHDL文件作为编辑区的活动窗口，然后你可以在FILE菜单选择Create/Updata,再在展开的二级菜单中选择第2项Create symbol file for current file。然后你就可以在原理图文件中调用这个文件所对应的元件符号了。
另外一种方法就是用COMPONENT元件例化语句在顶层文件里调用这个写好的VHDL文件，作为一个元件来使用了。例化语句可以找一本VHDL的书看看。

前不久正好闲着无聊编了个pwm的产生器，每按一次键改变一次占空比，可以实现占空比渐变，自己按需求改一下吧。频率和你晶振有关，我改了也没用。
library IEEE;
use IEEESTD_LOGIC_1164ALL;
use IEEESTD_LOGIC_ARITHALL;
use IEEESTD_LOGIC_UNSIGNEDALL;
entity PWMgenerator is
Port ( clk : in STD_LOGIC;
intr0 : in STD_LOGIC;
PWM : out STD_LOGIC);
end PWMgenerator;
architecture Behavioral of PWMgenerator is
signal count,preset,counter,setdest:integer range 0 to 1000:=0;
signal pwm_temp:STD_LOGIC;
signal changepreset:STD_LOGIC;
begin
process(clk)
begin
if clk'event and clk = '1' then
if count = 1000 then
count <= 0;
changepreset <= '1';
else
count <= count + 1;
changepreset <= '0';
end if;
end if;
end process;
process(count,preset)
begin
if count = 0 and preset > 0 then
pwm_temp <= '1';
elsif count = preset or preset = 0 then
pwm_temp <= '0';
else
null;
end if;
end process;
process(intr0,counter)
begin
if counter = 10 then
counter <= 0;
else
if intr0'event and intr0 = '1' then
counter <= counter + 1;
end if;
end if;
end process;
process(counter)
begin
case counter is
when 0 => setdest <= 0;
when 1 => setdest <= 100;
when 2 => setdest <= 200;
when 3 => setdest <= 300;
when 4 => setdest <= 400;
when 5 => setdest <= 500;
when 6 => setdest <= 600;
when 7 => setdest <= 700;
when 8 => setdest <= 800;
when 9 => setdest <= 900;
when 10 => setdest <= 1000;
when others => setdest <= 0;
end case;
end process;
process(setdest,count,preset,changepreset)
begin
if changepreset'event and changepreset = '1' then
if preset < setdest then
preset <= preset + 1;
elsif preset > setdest then
preset <= preset - 1;
else
null;
end if;
end if;
end process;
PWM <= pwm_temp;
end Behavioral;

先写一个divvhd文件作为元件：
library ieee;
use ieeestd_logic_1164all;
use ieeestd_logic_unsignedall;
entity div is
generic(n:integer :=48);
port (clk:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if (clk'event and clk='1' and clk'last_value ='0') then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;
再写一个dividervhd文件作为分频模块：
library ieee;
use ieeestd_logic_1164all;
entity divider is
port (clk0:in std_logic;
clk1M, clk4Hz:out std_logic);
end divider;
architecture structure of divider is
signal clk1MHz : std_logic;
component div
generic(n:integer :=48);
port (clk:in std_logic;
q:out std_logic);
end component;
begin
U1: div port map(clk => clk0, q => clk1MHz);
U2: div generic map(n => 250000) port map( clk => clk1MHz, q => clk4Hz);
clk1M <= clk1MHz;
end structure;

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