用的是VHDL
该程序实现的功能：设计一个至少4位的十进制计数器，具有加减计数功能和置数功能，并能通过数码管显示计数结果。减数为零时发声报警。加数为9999时报警
----------这个程序中clk接1KHZ时个位每秒变化一下-------------
-----------D:\VHDL\test\test\four\three\4位数码管级联\加计数----------
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
------------------------------------------
entity countup is
port(clk:in std_logic
clr:in std_logic
lad:in std_logic
en: in std_logic_vector(1 downto 0)
clkup:in std_logic
sel:out std_logic_vector(1 downto 0)
din:in std_logic_vector(3 downto 0)
pout:buffer std_logic_vector(7 downto 0)
speaker:out std_logic)
end entity countup
-----------------------------------------------
architecture art of countup is
SIGNAL dout:STD_LOGIC_VECTOR(3 DOWNTO 0)
SIGNAL dout0,dout1,dout2,dout3:STD_LOGIC_VECTOR(3 DOWNTO 0)
SIGNAL counter:std_logic_vector(1 downto 0)
begin
-----------------进程1---------------------------------------------------
one: --这个进程是数码管从0变到9之后，数码管的位置在依次变化
process(clkup)is
begin
if(en="00")then
if(clkup'event and clkup='1' )then
if clr='1' then dout0<="0000"dout1<="0000"dout2<="0000"dout3<="0000"
elsif lad='1' then dout0<=dindout1<=dindout2<=dindout3<=din
elsif(dout0>="1001")then dout0<="0000" ---------显示个位数字
if(dout1>="1001")then dout1<="0000" ---------显示十位数字
if(dout2>="1001")then dout2<="0000" --------显示百位数字
if(dout3>="1001")then dout3<="0000"----显示千位数字
else dout3<=dout3+1
end if
else dout2<=dout2+1
end if
else dout1<=dout1+1
end if
else dout0<=dout0+1
end if
end if
end if
end process
---------------------------------
process(clk) is
begin
if (clk'event and clk='1') then
if(dout0="1001" and dout1="1001" and dout2="1001" and dout3="1001")then
speaker<='1' else speaker<='0'
end if
end if
end process
------------------进程2---------------------------------------
two:
process(clk) is
begin
if (clk'event and clk='1') then
------------------------------------------------
counter<=counter+'1' ---
case counter is ---
when "00"=>dout<= dout1 ---
when "01"=>dout<= dout2 ---
when "10"=>dout<= dout3 ---
when "11"=>dout<= dout0 ---
when others=>NULL ---
end case ---
end if
---------------------------------
end process two
sel<=counter
-----------------进程3--------------------------------------------------
three: --这个进程是进入一个时钟dout就加1，而在数码管上显示的数字就相应的加1；直到数码管从1变化到9
process(dout)is
begin
case dout is
when "0000" => pout<="11111100"
when "0001" => pout<="01100000"
when "0010" => pout<="11011010"
when "0011" => pout<="11110010"
when "0100" => pout<="01100110"
when "0101" => pout<="10110110"
when "0110" => pout<="10111110"
when "0111" => pout<="11100100"
when "1000" => pout<="11111110"
when "1001" => pout<="11110110"
when others => pout<="00000001"
end case
end process three
-------------------------------------------------------------------
end architecture art
----------- D:\VHDL\test\test\four\three\4位数码管级联\减计数--------
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
------------------------------------------
entity countdn is
port(clk:in std_logic
clr:in std_logic
lad:in std_logic
en: in std_logic_vector(1 downto 0)
clkdn:in std_logic
sel:out std_logic_vector(1 downto 0)
din:in std_logic_vector(3 downto 0)
pout:buffer std_logic_vector(7 downto 0)
speaker:out std_logic)
end entity countdn
-----------------------------------------------
architecture art of countdn is
SIGNAL dout,pdout:STD_LOGIC_VECTOR(3 DOWNTO 0)
SIGNAL dout5,dout6,dout7,dout8:STD_LOGIC_VECTOR(3 DOWNTO 0)
SIGNAL counter:std_logic_vector(1 downto 0)
begin
-----------------进程1---------------------------------------------------
one1: --这个进程是数码管从0变到9之后，数码管的位置在依次变化
process(clkdn)is
begin
if en="01"then
if(dout6="0000" and dout7="0000" and dout8="0000" and dout5="0000")then
speaker<='1'else speaker<='0'
end if
if(clkdn'event and clkdn='1' )then
if clr='1' then dout5<="0000"dout6<="0000"dout7<="0000"dout8<="0000"
elsif lad='1' then dout5<=dindout6<=dindout7<=dindout8<=din
elsif(dout5="0000")then dout5<="1001" ---------显示个位数字
if(dout6="0000")then dout6<="1001" ---------显示十位数字
if(dout7="0000")then dout7<="1001" ---------显示百位数字
if(dout8="0000")then dout8<="1001" ---------显示千位数字
else dout8<=dout8-1
end if
else dout7<=dout7-1
end if
else dout6<=dout6-1
end if
else dout5<=dout5-1
end if
end if
end if
end process one1
--------------进程2-------------------------------------------
two:
process(clk) is
begin
if (clk'event and clk='1') then
------------------------------------------------
counter<=counter+'1' ---
case counter is ---
when "00"=>dout<= dout6 ---
when "01"=>dout<= dout7 ---
when "10"=>dout<= dout8 ---
when "11"=>dout<= dout5 ---
when others=>NULL ---
end case ---
end if
---------------------------------
end process two
sel<=counter
-----------------进程3--------------------------------------------------
three: --这个进程是进入一个时钟dout就加1，而在数码管上显示的数字就相应的加1；直到数码管从1变化到9
process(dout)is
begin
case dout is
when "0000" => pout<="11111100"
when "0001" => pout<="01100000"
when "0010" => pout<="11011010"
when "0011" => pout<="11110010"
when "0100" => pout<="01100110"
when "0101" => pout<="10110110"
when "0110" => pout<="10111110"
when "0111" => pout<="11100100"
when "1000" => pout<="11111110"
when "1001" => pout<="11110110"
when others => pout<="00000001"
end case
end process three
-------------------------------------------------------------------
end architecture art
------------pout2选1程序-----
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
------------------------------------------
entity pout is
port(a:in std_logic_vector(7 downto 0)
b:in std_logic_vector(7 downto 0)
c:out std_logic_vector(7 downto 0)
en:in std_logic_vector(1 downto 0))
end entity pout
-----------------------------------------------
architecture art of pout is
begin
process(en,a,b)is
begin
if en="00"then c<=a
else c<=b
end if
end process one1
end architecture art
------------sel2选1程序-----
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
------------------------------------------
entity sel is
port(a:in std_logic_vector(1 downto 0)
b:in std_logic_vector(1 downto 0)
c:out std_logic_vector(1 downto 0)
en:in std_logic_vector(1 downto 0))
end entity sel
-----------------------------------------------
architecture art of sel is
begin
process(en,a,b)is
begin
if en="00"then c<=a
else c<=b
end if
end process one1
end architecture art
你 所谓的并行，是不是说将一串8位二进制码，如上图中x输入转换为并行然后判断输入x是否等于预置值1010_1101？
还是题目中键4、3 并行输入信号•键 1、2 预置数据
每次并行检测2位，比如判断x输入两位是否等于10，后两位等于10，再两位等于11，最后两位等于01？
如果是这样，可以将x串行输入，进行个串并转换，例如用一个寄存器reg1[1:0]保存其值。
always @ (posedge clk or negedge rst)
if(!rst)
reg1 <= 2'h0
else
reg1 <= {x, reg1[1]}
然后对比reg1值是否等于预置值。
仅供参考，谢谢
你写testcase应该是想写个测试程序，那么对变量mask赋值应该放到initial块里面：initial
begin
mask=8'bx0x0x0x0
end
记住：测试程序里，对任何变量赋初值，都要放到initial块里。
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