求用vhdl语言做个全加器的程序

library ieee

use ieee.std_logic_1164.all

entity f_adder is

port(ain,bin,cin :in std_logic

cout,sum :out std_logic)

end entity f_adder

architecture f1 of f_adder is

component h_adder

port(a,b:in std_logic

co,so:out sud_logic)

end component

component or2a

port(a,b:in std_logic

c:out sud_logic)

end component

signal d,e,f:in std_logic

begin

u1:h_adder port(ain,bin,d,e)

u2:h_adder port(e,cin,f,sum)

u3:or2a port(d,f,cout)

end architecture f1

//一位二进制全加器

library ieee

use ieee.std_logic_1164.all

entity f_adder_4 is

port(a[3,b[3],c[3]] :in std_logic_vector(3 downto 0)

q[3],cout [3]:out std_logic_vector(3 downto 0))

end entity f_adder_4

architecture f2 of f_adder_4 is

component f_adder

port(ain,bin,cin :in std_logic

cout,sum :out std_logic)

end component

sigal a,b,c:std_logic

begin

f1:f_adder port map(a[0],b[0], ,q[0],a)

f2:f_adder port map(a[1],b[1],a,q[1],b)

f3:f_adder port map(a[2],b[2],b,q[2],c)

f4:f_adder port map(a[3],b[3],c,q[3],cout_4)

end architeture f2//四位全加器

假设a和b是两个本位 *** 作数，c_in是低位向本位的进位，sum是本位和，c_out是本位向高位的进位，都是std_logic类型的；input是进程体内声明的std_logic_vector类型的变量。只列出行为描述部分的代码，你需要用进程语句将其包装成并行语句：

input := c_in &b &a

case input is

when "000" =>sum <= '0'c_out <= '0'

when "001"|"010"|"100" =>sum <= '1'c_out <= '0'

when "011"|"110"|"101" =>sum <= '0'c_out <= '1'

when "111" =>sum <= '1'c_out <= '1'

when others =>sum <= '-'c_out <= '-'

end case

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