用verilog编写源代码和测试程序

下面的代码我已经用modelsim仿真过了，没有问题。

module count(out,clk,rst); //源程序

input clk,rst;

output[3:0] out;

reg[3:0] out;

initial out=4'd0;

always @(posedge clk or negedge rst)

begin

if(!rst) out=4'd0;

else

begin

out=out+4'd1;

if(out==4'd1||out==4'd6||out==4'd8) out=out+4'd1;

if(out==4'd5) out=out+4'd2;

end

end

endmodule

`timescale 1ns/1ns //测试程序

`include "countv"

module count_tp;

reg clk,rst;

wire[3:0] out;

parameter DELY=100;

count mycount(out,clk,rst);

always #(DELY/2) clk=~clk;

initial

begin

clk=0;rst=1;

#(DELY5) rst=0;

#DELY rst=1;

#(DELY20) $finish;

end

initial $monitor($time,,,"clk=%d rst=%d out=%d",clk,rst,out);

endmodule

这个是带使能端的3-8译码器，输出低电平有效！你可以参考一下！EDA实验上学的，希望对您有帮助。

library IEEE;

use IEEEstd_logic_1164all;

entity ls138 is

port (

A : in std_logic_vector (2 downto 0);

S1,S2,S3 : in std_logic;

Y : out std_logic_vector (7 downto 0)

);

end entity;

architecture ls138_arch of ls138 is

signal s : std_logic_vector(2 downto 0);

begin

S <= S1&S2&S3;

process(A, S)

begin

Y <= (others => '1');

if S="100" then

case A is

when "000" => Y <= "11111110"; -- 0

when "001" => Y <= "11111101"; -- 1

when "010" => Y <= "11111011"; -- 2

when "011" => Y <= "11110111"; -- 3

when "100" => Y <= "11101111"; -- 4

when "101" => Y <= "11011111"; -- 5

when "110" => Y <= "10111111"; -- 6

when "111" => Y <= "01111111"; -- 7

when others => NULL;

end case;

end if;

end process;

end architecture;

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