求fpga的verilog程序

always@(posedge clk)
begin
buffer<=buffer+1;
if(buffer==16'd500)
begin buffer<=0;t_clk<=~t_clk; end
end

always@(posedge t_clk)
begin
//if(reset==0) state<=2'b00;
case(state)
2'b00: begin CS<=0;WR<=0;RD<=1;state<=2'b01;read_data<=0; end
2'b01: begin
if(INTR==0) begin CS<=0;WR<=0;RD<=1;state<=2'b10;
read_data<=0;end
else state<=2'b00; end
2'b10: begin CS<=0;WR<=1;RD<=0;state<=2'b11;read_data<=1; end
2'b11: begin CS<=1;WR<=1;RD<=1;state<=2'b00;read_data<=0; end
endcase
end

always@(posedge t_clk)
begin
if(read_data==1) p<=data_in;
end

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