
library IEEE
use IEEE.Std_Logic_1164.ALL
entity decoder IS
port (in1 : in Std_Logic_Vector(2 downto 0)
out1,out2 : out Std_Logic_Vector(3 downto 0))
end decoder
architecture decoder38 of decoder is
begin
decoder:process(in1)
begin
case in1 is
when"000"=>out1<="00000001"
when"001"=>out1<="00000010"
when"010"=>out1<="00000100"
when"011"=>out1<="00001000"
when"100"=>out2<="00010000"
when"101"=>out2<禅岁="00100000"
when"110"桥袭弯=>out2<="01000000"
when"111"=>out2<="10000000"
when others=>null
end case
end process decoder
end decoder38
自己去实现敏闷吧,哈哈……
摘自动感居百科
欢迎分享,转载请注明来源:内存溢出
微信扫一扫
支付宝扫一扫
评论列表(0条)