* Module Name : lcd1602_driver
* Engineer : Crazy Bingo
* Target Device : EP2C8Q208C8
* Tool versions : Quartus II 11.0
* Create Date : 2011-6-25
* Revision : v1.0
* Description :
**************************************************/
module lcd1602_driver
(
input clk,
input rst_n,
output lcd_en, // lcd enable
output reg lcd_rs, // record,statement
output lcd_rw,
output reg [7:0] lcd_data,
output lcd_on,
output lcd_blon
)
parameter [127:0] line_rom1 = "I am CrazyBingo!"
parameter [127:0] line_rom2 = "Hello World*^_^*"
//--------------------------------------
reg [15:0] cnt
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 0
else
cnt <= cnt + 1'b1
end
assign lcd_on = 1'b1
assign lcd_blon = 1'b1
assign lcd_en = cnt[15] //lcd enable,keep same time
assign lcd_rw = 1'逗巧b0 /山此键/write only
wire cmd_flag = (cnt == 16'h7FFF) ? 1'b1 : 1'b0 //when lcd_en is steady,write a cmd
//---------------------------------------
// Gray code : 40 states
parameter IDLE = 8'h00 // IDLE
// lcd init
parameter DISP_SET = 8'h01 // display mode
parameter DISP_OFF = 8'h03 // off display
parameter CLR_SCR = 8'h02 // clear the lcd
parameter CURSOR_SET1 = 8'h06 // cursor set
parameter CURSOR_SET2 = 8'h07 // on display, cursor set
// display 1th line
parameter ROW1_ADDR = 8'h05
parameter ROW1_0 = 8'h04
parameter ROW1_1 = 8'h0C
parameter ROW1_2 = 8'h0D
parameter ROW1_3 = 8'h0F
parameter ROW1_4 = 8'h0E
parameter ROW1_5 = 8'h0A
parameter ROW1_6 = 8'h0B
parameter ROW1_7 = 8'h09
parameter ROW1_8 = 8'h08
parameter ROW1_9 = 8'h18
parameter ROW1_A = 8'h19
parameter ROW1_B = 8'h1B
parameter ROW1_C = 8'h1A
parameter ROW1_D = 8'h1E
parameter ROW1_E = 8'h1F
parameter ROW1_F = 8'h1D
/扒樱/ display 2th line
parameter ROW2_ADDR = 8'h1C
parameter ROW2_0 = 8'h14
parameter ROW2_1 = 8'h15
parameter ROW2_2 = 8'h17
parameter ROW2_3 = 8'h16
parameter ROW2_4 = 8'h12
parameter ROW2_5 = 8'h13
parameter ROW2_6 = 8'h11
parameter ROW2_7 = 8'h10
parameter ROW2_8 = 8'h30
parameter ROW2_9 = 8'h31
parameter ROW2_A = 8'h33
parameter ROW2_B = 8'h32
parameter ROW2_C = 8'h36
parameter ROW2_D = 8'h37
parameter ROW2_E = 8'h35
parameter ROW2_F = 8'h34
//---------------------------------------
reg [5:0] current_state, next_state
// FSM: always1
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
current_state <= IDLE
else if(cmd_flag)
current_state <= next_state
end
//---------------------------------------
// FSM: always2
always@*
begin
case(current_state)
// lcd init
IDLE : next_state = DISP_SET
DISP_SET : next_state = DISP_OFF
DISP_OFF : next_state = CLR_SCR
CLR_SCR : next_state = CURSOR_SET1
CURSOR_SET1 : next_state = CURSOR_SET2
CURSOR_SET2 : next_state = ROW1_ADDR
// display 1th line
ROW1_ADDR : next_state = ROW1_0
ROW1_0 : next_state = ROW1_1
ROW1_1 : next_state = ROW1_2
ROW1_2 : next_state = ROW1_3
ROW1_3 : next_state = ROW1_4
ROW1_4 : next_state = ROW1_5
ROW1_5 : next_state = ROW1_6
ROW1_6 : next_state = ROW1_7
ROW1_7 : next_state = ROW1_8
ROW1_8 : next_state = ROW1_9
ROW1_9 : next_state = ROW1_A
ROW1_A : next_state = ROW1_B
ROW1_B : next_state = ROW1_C
ROW1_C : next_state = ROW1_D
ROW1_D : next_state = ROW1_E
ROW1_E : next_state = ROW1_F
ROW1_F : next_state = ROW2_ADDR
// display 2th line
ROW2_ADDR : next_state = ROW2_0
ROW2_0 : next_state = ROW2_1
ROW2_1 : next_state = ROW2_2
ROW2_2 : next_state = ROW2_3
ROW2_3 : next_state = ROW2_4
ROW2_4 : next_state = ROW2_5
ROW2_5 : next_state = ROW2_6
ROW2_6 : next_state = ROW2_7
ROW2_7 : next_state = ROW2_8
ROW2_8 : next_state = ROW2_9
ROW2_9 : next_state = ROW2_A
ROW2_A : next_state = ROW2_B
ROW2_B : next_state = ROW2_C
ROW2_C : next_state = ROW2_D
ROW2_D : next_state = ROW2_E
ROW2_E : next_state = ROW2_F
ROW2_F : next_state = ROW1_ADDR
default : next_state = IDLE
endcase
end
//---------------------------------------
// FSM: always3
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
lcd_rs <= 0
lcd_data <= 8'hXX
end
else if(cmd_flag)
begin
// write statement
case(next_state)
IDLE : lcd_rs <= 0 //statement
//lcd init
DISP_SET : lcd_rs <= 0 //statement
DISP_OFF : lcd_rs <= 0 //statement
CLR_SCR : lcd_rs <= 0 //statement
CURSOR_SET1 : lcd_rs <= 0 //statement
CURSOR_SET2 : lcd_rs <= 0 //statement
// display 1th line
ROW1_ADDR : lcd_rs <= 0 //statement
ROW1_0 : lcd_rs <= 1 //record
ROW1_1 : lcd_rs <= 1 //record
ROW1_2 : lcd_rs <= 1 //record
ROW1_3 : lcd_rs <= 1 //record
ROW1_4 : lcd_rs <= 1 //record
ROW1_5 : lcd_rs <= 1 //record
ROW1_6 : lcd_rs <= 1 //record
ROW1_7 : lcd_rs <= 1 //record
ROW1_8 : lcd_rs <= 1 //record
ROW1_9 : lcd_rs <= 1 //record
ROW1_A : lcd_rs <= 1 //record
ROW1_B : lcd_rs <= 1 //record
ROW1_C : lcd_rs <= 1 //record
ROW1_D : lcd_rs <= 1 //record
ROW1_E : lcd_rs <= 1 //record
ROW1_F : lcd_rs <= 1 //record
// display 2th line
ROW2_ADDR : lcd_rs <= 0 //statement
ROW2_0 : lcd_rs <= 1 //record
ROW2_1 : lcd_rs <= 1 //record
ROW2_2 : lcd_rs <= 1 //record
ROW2_3 : lcd_rs <= 1 //record
ROW2_4 : lcd_rs <= 1 //record
ROW2_5 : lcd_rs <= 1 //record
ROW2_6 : lcd_rs <= 1 //record
ROW2_7 : lcd_rs <= 1 //record
ROW2_8 : lcd_rs <= 1 //record
ROW2_9 : lcd_rs <= 1 //record
ROW2_A : lcd_rs <= 1 //record
ROW2_B : lcd_rs <= 1 //record
ROW2_C : lcd_rs <= 1 //record
ROW2_D : lcd_rs <= 1 //record
ROW2_E : lcd_rs <= 1 //record
ROW2_F : lcd_rs <= 1 //record
endcase
// write lcd_data
case(next_state)
IDLE : lcd_data <= 8'hxx
//lcd init
DISP_SET : lcd_data <= 8'h38 //set 16X2,5X7 ,8 bits record
DISP_OFF : lcd_data <= 8'h08 //off display
CLR_SCR : lcd_data <= 8'h01 //clear lcd
CURSOR_SET1 : lcd_data <= 8'h06 //cursor set
CURSOR_SET2 : lcd_data <= 8'h0C //on display
// display 1th line
ROW1_ADDR : lcd_data <= 8'h80
ROW1_0 : lcd_data <= line_rom1[127:120]
ROW1_1 : lcd_data <= line_rom1[119:112]
ROW1_2 : lcd_data <= line_rom1[111:104]
ROW1_3 : lcd_data <= line_rom1[103: 96]
ROW1_4 : lcd_data <= line_rom1[ 95: 88]
ROW1_5 : lcd_data <= line_rom1[ 87: 80]
ROW1_6 : lcd_data <= line_rom1[ 79: 72]
ROW1_7 : lcd_data <= line_rom1[ 71: 64]
ROW1_8 : lcd_data <= line_rom1[ 63: 56]
ROW1_9 : lcd_data <= line_rom1[ 55: 48]
ROW1_A : lcd_data <= line_rom1[ 47: 40]
ROW1_B : lcd_data <= line_rom1[ 39: 32]
ROW1_C : lcd_data <= line_rom1[ 31: 24]
ROW1_D : lcd_data <= line_rom1[ 23: 16]
ROW1_E : lcd_data <= line_rom1[ 15: 8]
ROW1_F : lcd_data <= line_rom1[ 7: 0]
// display 2th line
ROW2_ADDR : lcd_data <= 8'hC0
ROW2_0 : lcd_data <= line_rom2[127:120]
ROW2_1 : lcd_data <= line_rom2[119:112]
ROW2_2 : lcd_data <= line_rom2[111:104]
ROW2_3 : lcd_data <= line_rom2[103: 96]
ROW2_4 : lcd_data <= line_rom2[ 95: 88]
ROW2_5 : lcd_data <= line_rom2[ 87: 80]
ROW2_6 : lcd_data <= line_rom2[ 79: 72]
ROW2_7 : lcd_data <= line_rom2[ 71: 64]
ROW2_8 : lcd_data <= line_rom2[ 63: 56]
ROW2_9 : lcd_data <= line_rom2[ 55: 48]
ROW2_A : lcd_data <= line_rom2[ 47: 40]
ROW2_B : lcd_data <= line_rom2[ 39: 32]
ROW2_C : lcd_data <= line_rom2[ 31: 24]
ROW2_D : lcd_data <= line_rom2[ 23: 16]
ROW2_E : lcd_data <= line_rom2[ 15: 8]
ROW2_F : lcd_data <= line_rom2[ 7: 0]
endcase
end
end
endmodule
板子的例程
`timescale 1ns / 1ps///////////////////////////////////////////////////////////////搏返///////////////////
// Company:anlogic
/兄宏/ Engineer: liguang
//
// Create Date:11:07:14 02/17/2014
// Design Name:
// Module Name:lcd1602
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////基尘饥///////////////////////////////////////////////////////////////////////////
module lcd1602(sys_clk,
sys_rstn ,
lcd_rs ,
lcd_rw ,
lcd_en ,
lcd_data
)
//输入输出信号定义
input sys_clk//系统时钟输入
input sys_rstn //系统复位信号，低电平有效
output lcd_rs //lcd的寄存器选择输出信号
output lcd_rw //lcd的读、写 *** 作选择输出信号
output lcd_en //lcd使能信号
output [7:0] lcd_data //lcd的数据总线（不进行读 *** 作，故为输出）
//寄存器定义
reglcd_rs
regclk_div
reg [17:0] delay_cnt
reg [7:0] lcd_data
reg [4:0] char_cnt
reg [7:0] data_disp
reg [9:0] state
parameteridle = 10'b000000000, //初始状态，下一个状态为CLEAR
clear = 10'b000000001, //清屏
set_function = 10'b000000010, //功能设置：8位数据接口/2行显示/5*8点阵字符
switch_mode = 10'b000000100, //显示开关控制：开显示，光标和闪烁关闭
set_mode = 10'b000001000, //输入方式设置：数据读写 *** 作后，地址自动加一/画面不动
shift= 10'b000010000, //光标、画面位移设置：光标向左平移一个字符位（光标显示是关闭的，所以实际上设置是看不出效果的）
set_ddram1 = 10'b000100000, //设置DDRAM的地址：第一行起始为0x00（注意输出时DB7一定要为1）
set_ddram2 = 10'b001000000, //设置DDRAM的地址：第二行为0x40（注意输出时DB7一定要为1）
write_ram1 = 10'b010000000, //数据写入DDRAM相应的地址
write_ram2 = 10'b100000000 //数据写入DDRAM相应的地址
assign lcd_rw = 1'b0 //没有读 *** 作，R/W信号始终为低电平
assign lcd_en = clk_div//E信号出现高电平以及下降沿的时刻与LCD时钟相同
//时钟分频
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
begin
delay_cnt<=18'd0
clk_div<=1'b0
end
else if(delay_cnt==18'd249999)
begin
delay_cnt<=18'd0
clk_div<=~clk_div
end
else
begin
delay_cnt<=delay_cnt+1'b1
clk_div<=clk_div
end
end
always@(posedge clk_div or negedge sys_rstn) //State Machine
begin
if(!sys_rstn)
begin
state <= idle
lcd_data <= 8'b0
char_cnt <= 5'd0
lcd_rs<=1'b0
end
else
begin
case(state)
idle: begin //初始状态
state <= clear
lcd_data <= 8'b0
end
clear: begin //清屏
state <= set_function
lcd_rs<=1'b0
lcd_data <= 8'b00000001
end
set_function: //功能设置(38H)：8位数据接口/2行显示/5*8点阵字符
begin
state <= switch_mode
lcd_rs<=1'b0
lcd_data <= 8'b00111000
end
switch_mode: //显示开关控制(0CH)：开显示，光标和闪烁关闭
begin
state <= set_mode
lcd_rs<=1'b0
lcd_data <= 8'b00001110
end
set_mode:begin //输入方式设置(06H)：数据读写 *** 作后，地址自动加一/画面不动
state <= shift
lcd_rs<=1'b0
lcd_data <= 8'b00000110
end
shift: begin //光标、画面位移设置(10H)：光标向左平移一个字符位（光标显示是关闭的，所以实际上设置是看不出效果的）
state <= set_ddram1
lcd_rs<=1'b0
lcd_data <= 8'b0001_0000
end
set_ddram1: //设置DDRAM的地址：第一行起始为00H（注意输出时DB7一定要为1）
begin
state <= write_ram1
lcd_rs<=1'b0
lcd_data <= 8'b1000_0011//Line1
end
set_ddram2: //设置DDRAM的地址：第二行为40H（注意输出时DB7一定要为1）
begin
state <= write_ram2
lcd_rs<=1'b0
lcd_data <= 8'b1100_0000//Line2
end
write_ram1:
begin
if(char_cnt <=5'd10)
begin
char_cnt <= char_cnt + 1'b1
lcd_rs<=1'b1
lcd_data <= data_disp
state <= write_ram1
end
else
begin
state <= set_ddram2
end
end
write_ram2:
begin
if(char_cnt <=5'd26)
begin
char_cnt <= char_cnt + 1'b1
lcd_rs<=1'b1
lcd_data <= data_disp
state <= write_ram2
end
else
begin
char_cnt <=5'd0
state <= shift
end
end
default: state <= idle
endcase
end
end
always @(char_cnt) //输出的字符
begin
case (char_cnt)
5'd0: data_disp = "W"
5'd1: data_disp = "e"
5'd2: data_disp = "l"
5'd3: data_disp = "c"
5'd4: data_disp = "o"
5'd5: data_disp = "m"
5'd6: data_disp = "e"
5'd7: data_disp = " "
5'd8: data_disp = "t"
5'd9: data_disp = "o"
5'd10: data_disp = " "
5'd11: data_disp = "A"
5'd12: data_disp = "n"
5'd13: data_disp = "l"
5'd14: data_disp = "o"
5'd15: data_disp = "g"
5'd16: data_disp = "i"
5'd17: data_disp = "c"
5'd18: data_disp = " "
5'd19: data_disp = "2"
5'd20: data_disp = "0"
5'd21: data_disp = "1"
5'd22: data_disp = "4"
5'd23: data_disp = "0"
5'd24: data_disp = "3"
5'd25: data_disp = "1"
5'd26: data_disp = "3"
default : data_disp =" "
endcase
end
endmodule
你只要把最后一个CASE语句里面welcome to anlogic 改掉就行了。（anlogic FPGA）
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