FPGA十分频程序，用VHDL写！！急求!!!

我这让握个是可以实现多个分频的。

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY DVF IS

PORT(CLK:IN STD_LOGIC ----时钟输入---

D:IN STD_LOGIC_VECTOR(7 DOWNTO 0) ----这个输入11111111-1010=1110101即是十分频----

FOUT:OUT STD_LOGIC)----对CLK十分频后的输出----

END

ARCHITECTURE ONE OF DVF IS

SIGNAL FULL:STD_LOGIC

SIGNAL F_T:STD_LOGIC

BEGIN

P_REG:PROCESS(CLK)

VARIABLE CNT8:STD_LOGIC_VECTOR(7 DOWNTO 0)

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CNT8="坦孙庆11111111"THEN

CNT8:=D

FULL<='1'

ELSE CNT8:=CNT8+1

FULL<='0'

END IF

END IF

END PROCESS P_REG

P_DIV:PROCESS(FULL)

VARIABLE CNT2:STD_LOGIC

BEGIN

IF FULL'EVENT AND FULL='1' THEN

CNT2:=NOT CNT2

IF CNT2='1' THEN

F_T<='凯野1'

ELSE F_T<='0'

END IF

END IF

END PROCESS P_DIV

FOUT<=F_T

END

其实具体来说是有很多细则的，我大体给你讲讲

在quartus 2中创建新工程之后，输入程序，然后编译，编译成功之后配置引脚，再综合。迹春然后蠢山点击下载，即进入对目标器件fpga的配置下载 *** 作，下姿档耐载成功就表示编程成功，这个时候，你就可以在板子上实现你程序文件的功能。

//www.21eda.com

//开发板型号:A-C8V4

//深圳市21EDA电子

//利用Verilog驱动LCD12864

//本实验是用LCD12864显示汉字。（LCD带字库）

//视频教程适合我们21EDA电子的所有学习板）

module LCD12864 (clk, rs, rw, en,dat)

input clk //系统时钟输入50M

output [7:0] dat //LCD的8位数据口

output rs,rw,en //LCD的控制脚

reg e

reg [7:0] dat

reg rs

reg [15:0] counter

reg [6:0] current,next

reg clkr

reg [1:0] cnt

//定义的一些状态机。

parameter set0=6'h0

parameter set1=6'h1

parameter set2=6'h2

parameter set3=6'h3

parameter set4=6'h4

parameter set5=6'h5

parameter set6=6'h6

parameter dat0=6'h7

parameter dat1=6'h8

parameter dat2=6'h9

parameter dat3=6'hA

parameter dat4=6'hB

parameter dat5=6'hC

parameter dat6=6'hD

parameter dat7=6'hE

parameter dat8=6'hF

parameter dat9=6'h10

parameter dat10=6'h12

parameter dat11=6'h13

parameter dat12=6'h14

parameter dat13=6'h15

parameter dat14=6'h16

parameter dat15=6'h17

parameter dat16=6'h18

parameter dat17=6'h19

parameter dat18=6'h1A

parameter dat19=6'h1B

parameter dat20=6'h1C

parameter dat21=6'h1D

parameter dat22=6'h1E

parameter dat23=6'h1F

parameter dat24=6'h20

parameter dat25=6'h21

parameter dat26=6'h22

parameter dat27=6'h23

parameter dat28=6'h24

parameter dat29=6'h25

parameter dat30=6'h26

parameter dat31=6'h27

parameter dat32=6'h28

parameter dat33=6'h29

parameter dat34=6'h2A

parameter dat35=6'h2B

parameter dat36=6'h2C

parameter dat37=6'h2E

parameter dat38=6'h2F

parameter dat39=6'h30

parameter dat40=6'h31

parameter dat41=6'h32

parameter dat42=6'h33

parameter dat43=6'h34

//////////////////////////////////////手缓纤///////

parameter nul=6'h35

always @(posedge clk) //哪源da de shi zhong pinlv

begin

counter=counter+1

if(counter==16'h000f)

clkr=~clkr

end

//////////////////////////////////毕仿//////////////

always @(posedge clkr)

begin

current=next

case(current)

set0: begin rs<=0dat<=8'h31next<=set1end //*设置8位格式,*

set1: begin rs<=0dat<=8'h0Cnext<=set2end //*整体显示,关光标,不闪烁*/

set2: begin rs<=0dat<=8'h06next<=set3end //*设定输入方式,增量不移位*/

set3: begin rs<=0dat<=8'h01next<=dat0end //*清除显示*/

dat0: begin rs<=1dat<=8'hc9next<=dat1end //显示第一行

dat1: begin rs<=1dat<=8'heenext<=dat2end

//上面是‘深’字的ACSII码值 C9EE

dat2: begin rs<=1dat<=8'hdbnext<=dat3end

dat3: begin rs<=1dat<=8'hdanext<=dat4end

//上面是‘圳’字的ACSII码值DBDA

dat4: begin rs<=1dat<=8'hcanext<=dat5end

dat5: begin rs<=1dat<=8'hd0next<=dat6end

//上面是‘市’字的ACSII码值CAD0

dat6: begin rs<=1dat<="2"next<=dat7end

dat7: begin rs<=1dat<="1"next<=dat8end

dat8: begin rs<=1dat<="E"next<=dat9end

dat9: begin rs<=1dat<="D"next<= dat10 end

dat10: begin rs<=1dat<=8'hB5next<=dat11end

dat11: begin rs<=1dat<=8'hE7next<=dat12end

//上面是‘电’字的ACSII码值B5E7

dat12: begin rs<=1dat<=8'hd7next<=dat13end

dat13: begin rs<=1dat<=8'hd3next<=set4end

//上面是‘子’字的ACSII码值D7D3

set4: begin rs<=0dat<=8'h90next<=dat14end //显示第二行

dat14: begin rs<=1dat<=8'hD0next<=dat15end

dat15: begin rs<=1dat<=8'hCDnext<=dat16end

//上面是‘型’字的ACSII码值D0CD

dat16: begin rs<=1dat<=8'hBAnext<=dat17end

dat17: begin rs<=1dat<=8'hC5next<=dat18end

//上面是‘号’字的ACSII码值BAC5

dat18: begin rs<=1dat<=":"next<=dat19end

dat19: begin rs<=1dat<="A"next<=dat20end

dat20: begin rs<=1dat<="-"next<=dat21end

dat21: begin rs<=1dat<="C"next<=dat22end

dat22: begin rs<=1dat<="8"next<=dat23end

dat23: begin rs<=1dat<="V"next<=dat24 end

dat24: begin rs<=1dat<="4"next<=dat25end

dat25: begin rs<=1dat<=" "next<=dat26end

dat26: begin rs<=1dat<=8'hbfnext<=dat27end

dat27: begin rs<=1dat<=8'hd8next<=dat28end

//上面是‘控’字的ACSII码值BFD8

dat28: begin rs<=1dat<=8'hd6next<=dat29end

dat29: begin rs<=1dat<=8'hc6next<=set5 end

//上面是‘制’字的ACSII码值D6C6

set5: begin rs<=0dat<=8'h88next<=dat30end //显示第三行

dat30: begin rs<=1dat<="L"next<=dat31end

dat31: begin rs<=1dat<="C"next<=dat32end

dat32: begin rs<=1dat<="D"next<=dat33end

dat33: begin rs<=1dat<="1"next<=dat34end

dat34: begin rs<=1dat<="2"next<=dat35 end

dat35: begin rs<=1dat<="8"next<=dat36 end

dat36: begin rs<=1dat<="6"next<=dat37 end

dat37: begin rs<=1dat<="4"next<=set6 end

set6: begin rs<=0dat<=8'h9Cnext<=dat38end //显示第四行

dat38: begin rs<=1dat<="G"next<=dat39end

dat39: begin rs<=1dat<="O"next<=dat40end

dat40: begin rs<=1dat<="O"next<=dat41end

dat41: begin rs<=1dat<="D"next<=dat42 end

dat42: begin rs<=1dat<="!"next<=dat43 end

dat43: begin rs<=1dat<="!"next<=nul end

nul: begin rs<=0 dat<=8'h00 // 把液晶的E 脚 拉高

if(cnt!=2'h2)

begin

e<=0next<=set0cnt<=cnt+1

end

else

begin next<=nule<=1

end

end

default: next=set0

endcase

end

assign en=clkr|e

assign rw=0

endmodule

verilog程序，自己翻译成VHDL吧

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