library ieee
use ieee.std_logic_1164.all
entity test is
port (
clk_i: in std_logic
rst_n_i : in std_logic
en_i : in std_logic
din_i: in std_logic
updata_o : out std_logic
dout0_o : out std_logic_vector(7 downto 0)
dout1_o : out std_logic_vector(7 downto 0)
dout2_o : out std_logic_vector(7 downto 0)
dout3_o : out std_logic_vector(7 downto 0)
dout4_o : out std_logic_vector(7 downto 0)
dout5_o : out std_logic_vector(7 downto 0)
dout6_o : out std_logic_vector(7 downto 0)
dout7_o : out std_logic_vector(7 downto 0)
)
end test
architecture behave of test is
signal loc_dout : std_logic_vector(63 downto 0) := (others =>'0')
signal dout0_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout1_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout2_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout3_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout4_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout5_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout6_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal dout7_temp : std_logic_vector(7 downto 0) := (others =>'0')
signal en_i_r : std_logic := '0'
begin -- behave
process (clk_i, rst_n_i)
begin -- process
if rst_n_i = '0' then -- asynchronous reset (active low)
loc_dout <= (others =>'0')
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if en_i = '漏锋1' then
loc_dout(0) <= din_i
loc_dout(63 downto 1) <= loc_dout(62 downto 0)
else
loc_dout <= loc_dout
end if
end if
end process
dout0_o <= dout0_temp
dout1_o <= dout1_temp
dout2_o <= dout2_temp
dout3_o <= dout3_temp
dout4_o <= dout4_temp
dout5_o <= dout5_temp
dout6_o <= dout6_temp
dout7_o <= dout7_temp
process (clk_i, rst_n_i)
begin -- process
if rst_n_i = '0' then -- asynchronous reset (active low)
dout0_temp <= (others =>'0')
dout1_temp <= (others =>'0')
dout2_temp <= (others =>'0')
dout3_temp <= (others =>'0')
dout4_temp <= (others =>'0')
dout5_temp <= (others =>'0')
dout6_temp <= (others =>'0')
dout7_temp <= (others =>'0')
updata_o <= '0'
en_i_r <= '0'
elsif clk_i'event and clk_i = '1' then -- rising clock edge
en_i_r <= en_i
if en_i = '1' and en_i_r = '0' then
updata_o <= '1'
dout0_temp <= loc_dout(7 downto 0)
dout1_temp <= loc_dout(15 downto 8)
dout2_temp <= loc_dout(23 downto 16)
dout3_temp <= loc_dout(31 downto 24)
dout4_temp <= loc_dout(39 downto 32)
dout5_temp <= loc_dout(47 downto 40)
dout6_temp <= loc_dout(55 downto 48)
dout7_temp <= loc_dout(63 downto 56)
else
updata_o <= '0'
dout0_temp <= dout0_temp
dout1_temp <= dout1_temp
dout2_temp <= dout2_temp
dout3_temp <= dout3_temp
dout4_temp <= dout4_temp
dout5_temp <= dout5_temp
dout6_temp <= dout6_temp
dout7_temp <= dout7_temp
end if
end if
end process
end behave
我用quartusⅡ凯敏已编译嫌链并且仿真都对的，我写的是0亮1灭，如果实际情况与这相反，你自己倒一下。LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_SIGNED.ALL
USE IEEE.numeric_std.all
ENTITY test IS
PORT (clock: in std_logic -----clock1加48MHz的信号
row: out std_logic_vector(0 to 7))
END test
ARCHITECTURE behave OF test IS
CONSTANT fp_clka:INTEGER:=12000000 ---扫描信号频率为2Hz
SIGNAL a: INTEGER RANGE 0 TO 12000001
signal saomiao :integer range 0 to 9
SIGNAL clka: std_logic
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF a<fp_clka then --clka
a<=a+1
clka<=clka
ELSE
a<=0
clka<= NOT clka
end if
end if
end process
process(clka)
BEGIN
IF rising_edge(clka) THEN
saomiao<=saomiao+1
if saomiao=9 then
saomiao<=0
end if
case saomiao is---'1'代表不亮,'0'代盯者枝表亮
when 0 =>row<="01111111"
when 1 =>row<="10111111"
when 2 =>row<="11011111"
when 3 =>row<="11101111"
when 4 =>row<="11110111"
when 5 =>row<="11111011"
when 6 =>row<="11111101"
when 7 =>row<="11111110"
when 8 =>row<="00000000"
when others =>row<="11111111"
END CASE
END IF
end process
END behave
1.process(CLK,CLRN)begin
if CLRN='0' then
Q[7:0]<=(others=>'0')
elsif CLK'event and CLK='1' then
if LDN='返好0' then
Q[7:0]<=D[7:0]
else
Q[7:0]<轿改=LDIN
end if
end if
end process
2.process(A,ENA,SEL)
begin
if ENA='1' then
case SEL is
when "0000" =>Y<=A[0]
when "0001 "=>Y<=A[1]
....
when "1111" =>漏帆铅 Y<=A[15]
when others => Y<=A[0]
end case
else
Y<='0'
end if
end process
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