when语句来实现，而对于外部输入的三个控制信号，也就相当于是一个计数器的控制信号，，你可以这样
entity
shuma
is
port(clk,reset:in
std_logic
start,cs:in
std_logic
disp1,disp2:out
std_logic_vector(7
downto
0)
led:out
std_logic)
end
entity
architecture
art
of
shuma
is
signal
count1:integer
range
0
to
......自已算
signal
count2,count3:integer
range
0
to
99
signal
clk_div,led_flag:std_logic
begin
process(clk,reset,count1)----首先进行时钟分频，分成1hz的；
begin
if
reset='1'
then
count1<=0
elsif
clk'event
and
clk='1'
then
if
count1=??
then
---这个倍数根据你的fpga板的时钟频率和1hz进行计算
count1<=0clk_div<=not
clk_div
else
count<=count+1
end
if
end
if
end
process
process(clk_div,reset,count2)
---数码管计数进程；
begin
if
reset='1'
then
count2<=0
elsif
clk_div'event
and
clk_div='1'
then
if
count2=99
then
led_flag<='1'--led亮的标志；
count2<=0
else
count2<=count2+1led_flag<='0'
end
if
end
if
end
process
process(count)--将计数的数值显示在数码管上,,用动态扫描法，对应关系
begin
自已查；
case
count
is
when
0=>disp1,disp2...
end
case
同样的led和测试程序
就是一个计数器，和上面类似，，，我要去上课啦，，希望以上那些可以帮助你！！！
VHDL语言编写一个七段译码电路（共阳极）LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY DecL7S IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) )
END
ARCHITECTURE one OF DecL7S IS
BEGIN
PROCESS( A )
BEGIN
CASE A(3 DOWNTO 0) IS
WHEN "0000" => LED7S <= "0111111" -- X“3F”0
WHEN "0001" => LED7S <= "0000110" -- X“06”1
WHEN "0010" => LED7S <= "1011011" -- X“5B”2
WHEN "0011" => LED7S <= "1001111" -- X“4F”3
WHEN "0100" => LED7S <= "1100110" -- X“66”4
WHEN "0101" => LED7S <= "1101101" -- X“6D”5
WHEN "0110" => LED7S <= "1111101" -- X“7D”6
WHEN "0111" => LED7S <= "0000111" -- X“07”7
WHEN "1000" => LED7S <= "1111111" -- X“7F”8
WHEN "1001" => LED7S <= "1101111" -- X“6F”9
WHEN "1010" => LED7S <= "1110111" -- X“77”10
WHEN "1011" => LED7S <= "1111100" -- X“7C”11
WHEN "1100" => LED7S <= "0111001" -- X“39”12
WHEN "1101" => LED7S <= "1011110" -- X“5E”13
WHEN "1110" => LED7S <= "1111001" -- X“79”14
WHEN "1111" => LED7S <= "1110001" -- X“71”15
WHEN OTHERS => NULL
END CASE
END PROCESS
END
这个一般有两种方法，一种是分奇偶分频，因为奇偶分频不一样，所以先判断是奇偶，然后再相应处理就可以了，另一种是一种整体算法思想，不需要判断奇偶数。。。顶层模块程序：
entity control_clk is
port(
Clk_i : in std_logic
Data_i : in std_logic_vector(4 downto 0)
Clk_div: out std_logic
)
end control_clk
architecture rlt_control of control_clk is
component odd_div is
port(
Clk_i : in std_logic
Data_i : in std_logic_vector(4 downto 0)
Clk_odd: out std_logic
)
end component
signal clk_odd : std_logic :='0'
component even_div is
port(
Clk_i : in std_logic
Data_i : in std_logic_vector(4 downto 0)
Clk_even : out std_logic
)
end component
signal clk_even : std_logic :='0'
signal odd_even : std_logic :='0'
begin
odd_u : odd_div
port map(
Clk_i =>Clk_i,
Data_i =>Data_i,
Clk_odd=>clk_odd
)
even_u : even_div
port map(
Clk_i =>Clk_i,
Data_i =>Data_i,
Clk_even=>clk_even
)
odd_even <= Data_i(0)
process(odd_even,clk_even,clk_odd)
begin
if odd_even ='0' then
Clk_div <= clk_even
else
Clk_div <= clk_odd
end if
end process
end rlt_control
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