数字钟设计 用VHDL语言实现 你怎么做的

源代码如下  自己把各个模块打好包  下面有个图   自己看看

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY TZKZQ IS

PORT(KEY: IN STD_LOGIC_VECTOR(1 DOWNTO 0)   --按键信号

CLK_KEY: IN STD_LOGIC       --键盘扫描信号

MAX_DAYS:IN STD_LOGIC_VECTOR(4 DOWNTO 0)  --本月最大天数

SEC_EN,MIN_EN,HOUR_EN,DAY_EN,MON_EN,YEAR_EN,WEEK_EN:OUT STD_LOGIC --异步并行置位使能

HOUR_CUR:IN STD_LOGIC_VECTOR(4 DOWNTO 0)

MIN_CUR,SEC_CUR:IN STD_LOGIC_VECTOR(5 DOWNTO 0)

YEAR_CUR:IN STD_LOGIC_VECTOR(6 DOWNTO 0)

MON_CUR :IN STD_LOGIC_VECTOR(3 DOWNTO 0)

DAY_CUR :IN STD_LOGIC_VECTOR(4 DOWNTO 0)

WEEK_CUR:IN STD_LOGIC_VECTOR(2 DOWNTO 0)

SEC,MIN:BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)

HOUR:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)

DAY :BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)

MON :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)

YEAR:BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0)

WEEK:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0))

END ENTITY TZKZQ

ARCHITECTURE ART OF TZKZQ IS

TYPE STATETYPE IS (NORMAL,SEC_SET,MIN_SET,HOUR_SET,DAY_SET,MON_SET,

YEAR_SET,WEEK_SET)

SIGNAL MODE:STATETYPE

BEGIN

PROCESS(KEY,CLK_KEY)

BEGIN

IF CLK_KEY'EVENT AND CLK_KEY='1' THEN

IF KEY="01" THEN

SEC_EN<='1'MIN_EN<='1'HOUR_EN<='1'

DAY_EN<='1'MON_EN<='1'YEAR_EN<='1'

WEEK_EN<='1'

CASE MODE IS

WHEN NORMAL =>  MODE<=SEC_SETSEC<=SEC_CURSEC_EN<='0'

WHEN SEC_SET => MODE<=MIN_SETMIN<=MIN_CURSEC_EN<='1'MIN_EN<='0'

WHEN MIN_SET => MODE<=HOUR_SETHOUR<=HOUR_CURMIN_EN<='1'HOUR_EN<='0'

WHEN HOUR_SET=> MODE<=DAY_SETDAY<=DAY_CURHOUR_EN<='1'DAY_EN<='0'

WHEN DAY_SET => MODE<=MON_SETMON<=MON_CURDAY_EN<='1'MON_EN<='0'

WHEN MON_SET => MODE<=YEAR_SETYEAR<=YEAR_CUR MON_EN<='1'

YEAR_EN<='0'

WHEN YEAR_SET => MODE<=WEEK_SETWEEK<=WEEK_CURYEAR_EN<='1'WEEK_EN<='0'

WHEN WEEK_SET => MODE<=NORMAL

END CASE

ELSIF KEY="10" THEN  --如果按下调整键，则自加

CASE MODE IS

WHEN SEC_SET => SEC_EN<='0'

--异步并行置位使能有效

IF SEC="111011" THEN SEC<="000000"

--如果秒计数到59，返回到0重新计数

ELSE SEC<=SEC+1 --否则继续计数

END IF

WHEN MIN_SET => MIN_EN<='0'

IF MIN="111011" THEN MIN<="000000"

ELSE MIN<=MIN+1

END IF

WHEN HOUR_SET=> HOUR_EN<='0'

IF HOUR="11000" THEN                      HOUR<="00000"

ELSE HOUR<=HOUR+1

END IF

WHEN DAY_SET => DAY_EN<='0'

IF DAY=MAX_DAYS THEN DAY<="00001"

ELSE DAY<=DAY+1

END IF

WHEN WEEK_SET=> WEEK_EN<='0'

IF WEEK="111" THEN WEEK<="001"

ELSE WEEK<=WEEK+1

END IF

WHEN OTHERS=>NULL

END CASE

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)

CO: OUT STD_LOGIC)

END ENTITY CNT60

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000"CO<='1'

ELSE

NUM<=NUM+1CO<='0'

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT60 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(5 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(5 DOWNTO 0)

CO: OUT STD_LOGIC)

END ENTITY CNT60

ARCHITECTURE ART OF CNT60 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111011" THEN --59

NUM<="000000"CO<='1'

ELSE

NUM<=NUM+1CO<='0'

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT24 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(4 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)

CO: OUT STD_LOGIC)

END ENTITY CNT24

ARCHITECTURE ART OF CNT24 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="11000" THEN --24

NUM<="00000"CO<='1'

ELSE

NUM<=NUM+1CO<='0'

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT30 IS

PORT(LD:IN STD_LOGIC

CLK:IN STD_LOGIC

NIAN:IN STD_LOGIC_VECTOR(6 DOWNTO 0)

YUE :IN STD_LOGIC_VECTOR(3 DOWNTO 0)

DATA:IN STD_LOGIC_VECTOR(4 DOWNTO 0)

NUM:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)

MAX_DAYS:OUT STD_LOGIC_VECTOR(4 DOWNTO 0)

CO:OUT STD_LOGIC)

END ENTITY CNT30

ARCHITECTURE ART OF CNT30 IS

SIGNAL TOTAL_DAYS:STD_LOGIC_VECTOR(4 DOWNTO 0)

BEGIN

PROCESS(CLK,LD) IS

VARIABLE IS_RUNNIAN:STD_LOGIC

BEGIN

CASE NIAN IS

WHEN "0000000" => IS_RUNNIAN:='1'     --0

WHEN "0000100" => IS_RUNNIAN:='1'  --4

WHEN "0001000" => IS_RUNNIAN:='1'  --8

WHEN "0001100" => IS_RUNNIAN:='1'  --12

WHEN "0010000" => IS_RUNNIAN:='1'  --16

WHEN "0010100" => IS_RUNNIAN:='1'  --20

WHEN "0011000" => IS_RUNNIAN:='1'  --24

WHEN "0011100" => IS_RUNNIAN:='1'  --28

WHEN "0100000" => IS_RUNNIAN:='1'  --32

WHEN "0100100" => IS_RUNNIAN:='1'  --36

WHEN "0101000" => IS_RUNNIAN:='1'  --40

WHEN "0101100" => IS_RUNNIAN:='1'  --44

WHEN "0110000" => IS_RUNNIAN:='1'  --48

WHEN "0110100" => IS_RUNNIAN:='1'  --52

WHEN "0111000" => IS_RUNNIAN:='1'  --56

WHEN "0111100" => IS_RUNNIAN:='1'  --60

WHEN "1000000" => IS_RUNNIAN:='1'  --64

WHEN "1000100" => IS_RUNNIAN:='1'  --68

WHEN "1001000" => IS_RUNNIAN:='1'  --72

WHEN "1001100" => IS_RUNNIAN:='1'  --76

WHEN "1010000" => IS_RUNNIAN:='1'  --80

WHEN "1010100" => IS_RUNNIAN:='1'  --84

WHEN "1011000" => IS_RUNNIAN:='1'  --88

WHEN "1011100" => IS_RUNNIAN:='1'  --92

WHEN "1100000" => IS_RUNNIAN:='1'  --96

WHEN OTHERS    => IS_RUNNIAN:='0'

END CASE

CASE YUE IS

WHEN "0001"  => TOTAL_DAYS<="11111" --1

WHEN "0011"  => TOTAL_DAYS<="11111"  --3

WHEN "0101"  => TOTAL_DAYS<="11111"  --5

WHEN "0111"  => TOTAL_DAYS<="11111"  --7

WHEN "1000"  => TOTAL_DAYS<="11111"  --8

WHEN "1010"  => TOTAL_DAYS<="11111"  --10

WHEN "1100"  => TOTAL_DAYS<="11111"  --12

WHEN "0100"  => TOTAL_DAYS<="11110"  --4

WHEN "0110"  => TOTAL_DAYS<="11110"  --6

WHEN "1001"  => TOTAL_DAYS<="11110"  --9

WHEN "1011"  => TOTAL_DAYS<="11110"  --11

WHEN "0010"  =>

IF (IS_RUNNIAN='1') THEN

TOTAL_DAYS<="11101"

ELSE

TOTAL_DAYS<="11100"

END IF

WHEN OTHERS=>NULL

END CASE

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

MAX_DAYS<=TOTAL_DAYS

IF NUM=TOTAL_DAYS THEN  --99

NUM<="00001"CO<='1'

ELSE

NUM<=NUM+1CO<='0'

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT7 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(2 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0))

END ENTITY CNT7

ARCHITECTURE ART OF CNT7 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="111" THEN --7

NUM<="000"

ELSE

NUM<=NUM+1

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT12 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)

CO: OUT STD_LOGIC)

END ENTITY CNT12

ARCHITECTURE ART OF CNT12 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100" THEN --12

NUM<="0000"CO<='1'

ELSE

NUM<=NUM+1CO<='0'

END IF

END IF

END PROCESS

END ARCHITECTURE ART

LIBRARY IEEE

USE IEEE.STD_LOGIC_1164.ALL

USE IEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CNT99 IS

PORT(LD: IN STD_LOGIC

CLK: IN STD_LOGIC

DATA: IN STD_LOGIC_VECTOR(6 DOWNTO 0)

NUM: BUFFER STD_LOGIC_VECTOR(6 DOWNTO 0))

END ENTITY CNT99

ARCHITECTURE ART OF CNT99 IS

BEGIN

PROCESS(CLK,LD) IS

BEGIN

IF(LD='0') THEN

NUM<=DATA

ELSIF CLK'EVENT AND CLK='1' THEN

IF NUM="1100011" THEN --12

NUM<="0000000"

ELSE

NUM<=NUM+1

END IF

END IF

END PROCESS

END ARCHITECTURE ART

键盘输入的的确是四位二进制编码没错，你可以在百度里搜索“FPGA键盘输入”，出来的第一个博客讲的就是这个内容。数码管左移很简单，每次判断完有按键按下之后，开始进行动态扫描，比如从1到3无限循环，1的时候显示个位数，2的时候显示十位数，具体程序如下

process(clk2)--数码管动态显示的程序

variable countx: integer range 0 to1024 :=0--计数值，用于添加闪烁

variable count0: integer range 0 to10 :=0--数码管显示个位数

variable count1: integer range 0 to10 :=0--数码管显示十位数

variable play: integer range 0 to 9:=0

variable countplay: integer range 0to 50 :=0

variable countplay1: integer range 0to 3 :=0

variable flash:integer range 0 to15:=0

begin

if(clk2' event and clk2= '1') then

countx := countx + 1

countplay := countplay + 1

if(countx = 1024) then

countx := 0

end if

if (T>=50) then --判断十位数的大小

count1:=5

elsif (T>=40) then

count1:=4

elsif (T>=30) then

count1:=3

elsif (T>=20) then

count1:=2

elsif (T>=10) then

count1:=1

else

count1:=0

end if

count0:=T-10*count1

if(countplay = 5) then

countplay := 0

countplay1 := countplay1 + 1

if(countplay1 = 3) then

countplay1 := 0

end if

end if

if (stop='1'and countx<=200 )then --闪烁信号所加的位置

wx<="11111111"

else

if(countplay1 = 0) then wx <="11111110"play:= count0--位选信号

end if

if (countplay1 = 1) then wx <="11111101"play:= count1

end if

end if

case play is--数码管段选信号

when 0 =>dx <="11000000"

when 1 =>dx <="11111001"

when 2 =>dx <="10100100"

when 3 =>dx <="10110000"

when 4 =>dx <= "10011001"

when 5 =>dx<="10010010"

when 6 =>dx <="10000010"

when 7 =>dx <="11111000"

when 8 =>dx <="10000000"

when 9 =>dx <="10010000"

--when others =>Y <="00000000"

end case

end if

end process

（这个程序里面一个闪烁的信号，你没用的话可以直接去掉，不影响其他部分）

你可以把4对分成两组，当按键按一下，就换一组显示，或者两个按键控制，按下哪个按键就显示哪个，，，给你一个特例程序分别是以上两种方法 的，你可以参考参考，，，

port(input1,input2:in std_logic_vector(7 downto 0)；--两组数据

key:in std_logic；--按键(应该是消抖后的）

output:out std_logic)；

end entity；

architecture art of ... is

begin

process(input1,input2,key)

variable cnt:std_logic；；

begin

if key'event and key='1' then ---假设按键是高电平有效；

cnt:=not cnt；

if cnt='0' then

output<=input1；

else output<=input2；

end if；

end if；。

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