用vhdl语言编写【篮球比赛数字记分牌】

vhdl语言实现【篮球比赛数字记分牌】，源程序如下，仿真结果及电路连接图如图所示

--由于两个队的记分牌是一样的，所以这里只设计一个队（命名为A队）的记分牌，另一个队的记

--分牌可直接调用这个模块就可以了。

LIBRARY ieee

use ieee.std_logic_1164.all

use ieee.std_logic_arith.all

use ieee.std_logic_unsigned.all

--*-------------------------------------------------------*--

ENTITY counter_A IS

PORT(clk       : in std_logic  --时钟

     clr       : in std_logic  --异步清零信号

     score_A_2 : in std_logic  --进球得分2分

     score_A_1 : in std_logic  --发球得分1分

     error_A_2 : in std_logic  --纠错后减掉2分

     error_A_1 : in std_logic  --纠错后减掉1分

     led7_1  : out std_logic_vector(6 downto 0)--显示个位的数码管

     led7_2  : out std_logic_vector(6 downto 0)--显示十位的数码管

     led7_3  : out std_logic_vector(6 downto 0))--显示百位的数码管

End counter_A

--*------------------------------------------------------*--

ARCHITECTURE arch OF counter_A IS

signal Q1 : std_logic_vector(3 downto 0) --个位计数器

signal Q2 : std_logic_vector(3 downto 0) --十位计数器

signal Q3 : std_logic_vector(3 downto 0) --百位计数器

begin

P1 : process(clk,clr)

begin

if clr='0' then     --clr=0时计数器清零；

Q1 <= "0000"

Q2 <= "0000"

Q3 <= "0000"

elsif clk'event and clk='0' then

if score_A_2 ='1' then

Q1 <= Q1+"0010"

if Q1="1000" then

Q1 <= "0000"

Q2 <= Q2+1

if Q2="1001" then

Q2 <= "0000"

Q3 <= Q3+1

end if

elsif Q1="1001" then

Q1 <= "0001"

Q2 <= Q2+1

if Q2="1001" then

Q2 <= "0000"

Q3 <= Q3+1

end if

end if

elsif score_A_1 ='1' then

Q1 <= Q1 + "0001"

if Q1="1001" then

Q1 <= "0000"

Q2 <= Q2+1

if Q2="1001" then

Q2 <= "0000"

Q3 <= Q3+1

end if

end if

elsif error_A_2 ='1' then

Q1 <= Q1 - "0010"

if Q1="0001" then

Q1 <= "1001"

Q2 <= Q2-1

elsif Q1="0000" then

Q1 <="1000"

Q2 <= Q2-1

end if

elsif error_A_1 ='1' then

Q1 <= Q1 - "0001"

if Q1="0000" then

Q1 <= "1001"

Q2 <= Q2-1

end if

end if

end if

end process P1

--*------------------------------------------------------------

led1 :  process(Q1,clr) --个位数码管显示进程段

begin

if clr='0' then

led7_1 <= "0000000"

else

case Q1 is

when"0000"=>led7_1<="1111110"

when"0001"=>led7_1<="0110000"

when"0010"=>led7_1<="1101101"

when"0011"=>led7_1<="1111001"

when"0100"=>led7_1<="0110011"

when"0101"=>led7_1<="1011011"

when"0110"=>led7_1<="1011111"

when"0111"=>led7_1<="1110000"

when"1000"=>led7_1<="1111111"

when"1001"=>led7_1<="1111011"

when others=>led7_1<="0000000"

        end case

end if

end process led1

--*------------------------------------------------------------

led2 :  process(Q2,clr)  --十位数码管显示进程段

begin

if clr='0' then

led7_2 <= "0000000"

else

case Q2 is

when"0000"=>led7_2<="1111110"

when"0001"=>led7_2<="0110000"

when"0010"=>led7_2<="1101101"

when"0011"=>led7_2<="1111001"

when"0100"=>led7_2<="0110011"

when"0101"=>led7_2<="1011011"

when"0110"=>led7_2<="1011111"

when"0111"=>led7_2<="1110000"

when"1000"=>led7_2<="1111111"

when"1001"=>led7_2<="1111011"

when others=>led7_2<="0000000"

end case

end if

end process led2

--*------------------------------------------------------------

led3 :  process(Q3,clr)   --百位数码管显示进程段

begin

if clr='0' then

led7_3 <= "0000000"

else

case Q3 is

when"0000"=>led7_3<="1111110"

when"0001"=>led7_3<="0110000"

when"0010"=>led7_3<="1101101"

when"0011"=>led7_3<="1111001"

when"0100"=>led7_3<="0110011"

when"0101"=>led7_3<="1011011"

when"0110"=>led7_3<="1011111"

when"0111"=>led7_3<="1110000"

when"1000"=>led7_3<="1111111"

when"1001"=>led7_3<="1111011"

when others=>led7_3<="0000000"

end case

end if

end process led3

end arch

--*-------------------------------------------------------*--

LIBRARY IEEE

USEIEEE.STD_LOGIC_1164.ALL

USEIEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CLOCK IS

PORT( CLK: IN STD_LOGIC

DOUT1:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----秒钟个位输出

DOUT2:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----秒钟时位输出

DOUT3:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----分钟个位输出

DOUT4:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----分钟时位输出

DOUT5:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----时钟个位输出

DOUT6: BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----时钟十位输出

CO: OUT STD_LOGIC)

-- LED1: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)

-- LED2: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)

-- LED3: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)

-- LED4: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)

-- LED5: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)

-- LED6: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))

END CLOCK

ARCHITECTURECK OF CLOCK IS

SIGNAL CO1: STD_LOGIC

SIGNAL CO2: STD_LOGIC

SIGNAL QOUT1: STD_LOGIC_VECTOR( 3 DOWNTO 0)

SIGNAL QOUT2: STD_LOGIC_VECTOR( 3 DOWNTO 0)

SIGNAL QOUT3: STD_LOGIC_VECTOR( 3 DOWNTO 0)

SIGNAL QOUT4: STD_LOGIC_VECTOR( 3 DOWNTO 0)

SIGNAL QOUT5: STD_LOGIC_VECTOR( 3 DOWNTO 0)

SIGNAL QOUT6: STD_LOGIC_VECTOR( 3 DOWNTO 0)

-- COMPONENT LED IS

--PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0)

--QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))

--END COMPONENT

BEGIN

U1: PROCESS( CLK ) ---秒钟进程表

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF QOUT1 = 9 THEN

IF QOUT2=5 THEN

CO1 <= '1'

QOUT1 <="0000"

QOUT2 <="0000"

ELSE

QOUT1 <= "0000"

CO1 <='0'

QOUT2 <= QOUT2+1

END IF

ELSE

QOUT1 <= QOUT1+1

CO1 <= '0'

END IF

END IF

END PROCESS

DOUT1 <= QOUT1

DOUT2 <= QOUT2

U2: PROCESS(CO1) --分钟进程表

BEGIN

IF CO1'EVENT AND CO1='1' THEN

IF QOUT3 = 9 THEN

IF QOUT4=5 THEN

CO2 <= '1'

QOUT3 <="0000"

QOUT4 <="0000"

ELSE

QOUT3 <= "0000"

CO2 <='0'

QOUT4 <= QOUT4+1

END IF

ELSE

QOUT3 <= QOUT3+1

CO2 <= '0'

END IF

END IF

END PROCESS

DOUT3 <= QOUT3

DOUT4 <= QOUT4

U3: PROCESS(CO2) --分钟进程表

BEGIN

IF CO2'EVENT AND CO2='1' THEN

IF QOUT5 = 3 THEN

IF QOUT6=2 THEN

CO <= '1'

QOUT5 <="0000"

QOUT6 <="0000"

ELSE

QOUT5 <= "0000"

CO <='0'

QOUT6 <= QOUT6+1

END IF

ELSE

QOUT5 <= QOUT5+1

CO <= '0'

END IF

END IF

END PROCESS

DOUT5 <= QOUT5

DOUT6 <= QOUT6

--L1: LEDPORT MAP( DOUT1,LED1)

--L2: LEDPORT MAP( DOUT2,LED2)

--L3: LEDPORT MAP( DOUT3,LED3)

--L4: LEDPORT MAP( DOUT4,LED4)

--L5: LEDPORT MAP( DOUT5,LED5)

--L6: LEDPORT MAP( DOUT6,LED6)

END ARCHITECTURE CK

下面是共阴数码管的程序

LIBRARY IEEE

USEIEEE.STD_LOGIC_1164.ALL

USEIEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY LED IS ------共阴管

PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0)

QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))

END LED

ARCHITECTURE DISPLAY OF LED IS

BEGIN

WITH QIN SELECT

QOUT <= "11111110" WHEN "0000",

"01100000" WHEN "0001",

"11011010" WHEN "0010",

"11110010" WHEN "0011",

"01100110" WHEN "0100",

"10110110" WHEN "0101",

"00111110" WHEN "0110",

"11100000" WHEN "0111",

"11111110" WHEN "1000",

"11100110" WHEN "1001",

"00000000" WHEN OTHERS

END ARCHITECTURE DISPLAY

这个是一个时钟程序；再加一个数码管显示就可以到数码管上显示出来了

这个电子钟是用六十进制和二十四进制写的

顶层文件：

LIBRARY IEEE

USEIEEE.STD_LOGIC_1164.ALL

USEIEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY CLOCK IS

PORT( CLK: IN STD_LOGIC

CLR: IN STD_LOGIC

RES: IN STD_LOGIC

RES1 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0)--秒钟重调

RES2 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0)--分钟重调

RES3 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)--时钟重调

QO1 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)-- 秒钟输出

QO2 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)--分钟输出

QO3 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)--时钟输出

CO3 : OUT STD_LOGIC)

END ENTITY CLOCK

ARCHITECTURE TIME OF CLOCK IS

SIGNAL CO1: STD_LOGIC

SIGNAL CO2: STD_LOGIC

COMPONENT COUNT60 IS

PORT ( CLK : IN STD_LOGIC

CLR : IN STD_LOGIC

RES : IN STD_LOGIC

QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0)

QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)

CO : OUT STD_LOGIC )

END COMPONENT

COMPONENT COUNT24 IS

PORT ( CLK : IN STD_LOGIC

CLR : IN STD_LOGIC

RES : IN STD_LOGIC

QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)

QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)

CO : OUT STD_LOGIC )

END COMPONENT

BEGIN

U1: COUNT60

PORT MAP( CLK,CLR,RES,RES1,QO1,CO1)

U2: COUNT60

PORT MAP( CO1,CLR,RES,RES2,QO2,CO2)

U3: COUNT24

PORT MAP( CO2,CLR,RES,RES3,QO3,CO3)

END ARCHITECTURE TIME

下面是二十四进制计数

LIBRARY IEEE

USEIEEE.STD_LOGIC_1164.ALL

USEIEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY COUNT24IS

PORT ( CLK : IN STD_LOGIC

CLR : IN STD_LOGIC

RES : IN STD_LOGIC

QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)

QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)

CO : OUT STD_LOGIC )

END ENTITY COUNT24

ARCHITECTURE BHV OF COUNT24 IS

SIGNAL Q : STD_LOGIC_VECTOR( 4 DOWNTO 0)

BEGIN

PROCESS( CLK, CLR, RES)

BEGIN

IF CLR = '1' THEN

Q <="00000"

ELSIF CLK'EVENT AND CLK='1' THEN

IF RES ='1' THEN

Q <=QI

ELSIF Q = 23 THEN

Q <="00000"

CO <='1'

ELSE Q <= Q+1

CO<='0'

END IF

END IF

END PROCESS

QO <= Q

END ARCHITECTURE BHV

下面是六十进制计数

LIBRARY IEEE

USEIEEE.STD_LOGIC_1164.ALL

USEIEEE.STD_LOGIC_UNSIGNED.ALL

ENTITY COUNT60 IS

PORT ( CLK : IN STD_LOGIC

CLR : IN STD_LOGIC

RES : IN STD_LOGIC

QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0)

QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)

CO : OUT STD_LOGIC )

END ENTITY COUNT60

ARCHITECTURE COUNT OF COUNT60 IS

SIGNAL Q : STD_LOGIC_VECTOR( 5 DOWNTO 0)

BEGIN

PROCESS (CLK,CLR,RES)

BEGIN

IF CLR = '1'THEN

Q <= "000000"

ELSIF CLK'EVENT AND CLK = '1' THEN

IF RES ='1' THEN

Q <= QIN

ELSIF Q = 59 THEN

Q <= "000000"

CO <='1'

ELSE

Q <=Q + 1

CO <= '0'

END IF

END IF

END PROCESS

QOUT <= Q

END ARCHITECTURE

这个是用两个60进制和一个24进制做的

用vhdl设计秒表全功略！

根据要求, 秒表的设计要有三个输入端：runstop,rst和clk. runstop是开关, 按一下开始计时, 再按一下停止计时, 显示时间. 可以使用一个T触发器来实现. 当我们把T触发器的T端接高电平时, 它将实现翻转功能. 然后用输入端口runstop 来控制, 当runstop 被按一下, 一个时钟到来, T触发器就进行一次翻转. 我们也可以用D触发器来代替T触发器, 需要用一个反馈信号, 将输出的信号反馈到D端口. Rst 是复位, 当按下rst 时, 秒表的显示变为0. Clk是时钟, 实验中的时钟信号是250KHZ,为了实现秒表的正确计时功能, 需要进行2500分频. 所以clk首先就应该接到一个分频器, 然后再为其他模块提供时钟. 接着我们把秒表划分为以下几个模块：分频器, 计数器, T触发器, 扫描器, 八选一选择器, 七段译码器, 另外还有一个模块要在分, 秒和毫秒之间做一个划分（BAR）. 计数器的功能是要实现毫秒,秒,分的计数,比较麻烦.我们再将它分成几个模块, 可以是六进制的计数器和十进制的计数器进行级联来实现.也可以是用100进制的计数器和60进制的计数器进行级联. 我两种方法都尝试了一下.发现后一种方法编程要复杂的多, 级联的时候可以稍微简单一些. 因为D触发器,八选一选择器是程序包里有的，所以可以不编. 把这些模块都编好了以后要做的就是把他们连在一起. 有两种方法. 一是用画图的方法, 二是用编程的方法, 用port map语句. 同样, 这两种方法我也都尝试了. 我觉得用画图的方法要简单一些.

1程序如下：分频器： library ieeeuse ieee.std_logic_1164.alluse ieee.std_logic_unsigned.allentity df is port(clkin:in std_logicdout:out std_logic)

endarchitecture behavioral of df is begin process(clkin) variable df: std_logic_vector(7 downto 0):="00000000"begin if (clkin'event and clkin='1')then if df/="11111010" then df:=df+1else df:="00000001"end ifend ifdout<=df(7)end processend behavioral扫描器： library ieeeuse ieee.std_logic_1164.alluse ieee.std_logic_unsigned.all

entity scan is port(clk:in std_logics:out std_logic_vector(2 downto 0))end scan

architecture behavioral of scan is variable scan:std_logic_vector(2 downto 0)begin process(clk) begin if(clk'event and clk='1')then scan:=scan+1end ifs<=scanend processend behavioral七段译码器： library ieeeuse ieee.std_logic_1164.all

entity bcd is port(o:in std_logic_vector(3 downto 0)q:out std_logic_vector(6 downto 0))end bcd

architecture behavioral of bcd is begin process(o) begin case o is when"0000"=>q<="0111111"when"0001"=>q<="0000110"when"0010"=>q<="1011011"when"0011"=>q<="1001111"when"0100"=>q<="1100110"when"0101"=>q<="1101101"when"0110"=>q<="1111101"when"0111"=>q<="0100111"when"1000"=>q<="1111111"when"1001"=>q<="1101111"when others=>q<="0000000"end caseend processend behavioral当然，以上的100进制和60进制计数器的设计过于复杂，可以由六进制和十进制的计数器级联代替，程序如下：六进制： library ieeeuse ieee.std_logic_1164.alluse ieee.std_logic_unsigned.allentity c6 is port(count:out std_logic_vector(3 downto 0)cout:out std_logiccin,rst,clk:in std_logic)end c6architecture behavioral of c6 is signal counter:std_logic_vector(2 downto 0)begin process(clk,rst) begin if rst='1'then counter<="000"cout<='0'elsif clk'event and clk='1' then if cin='1' then if counter="101"then counter<="000"cout<='1'else counter<=counter+"001"cout<='0'end ifend ifend ifend processcount(2 downto 0)<=countercount(3)<='0'end behavioral

十进制： library ieeeuse ieee.std_logic_1164.alluse ieee.std_logic_unsigned.all

entity c10 is port(count:out std_logic_vector(3 downto 0)cout:out std_logiccin,rst,clk:in std_logic)end c10

architecture behavioral of c10 is signal counter:std_logic_vector(3 downto 0)begin process(clk,rst) begin if rst='1'then counter<="0000"cout<='0'elsif clk'event and clk='1' then if cin='1' then if counter="1001"then counter<="0000"cout<='1'else counter<=counter+"0001"cout<='0'end ifend ifend ifend processcount<=counterend behavioral

最后用画图讲这些模块连接起来.

---