麻烦这个VHDL程序出现以下问题怎么改？谢谢了！

进程描述错误：

PROCESS

BEGIN

CLK<='0'

CLK<='1'

END

PROCESS

进程语句应当有敏感信号表或者WAIT语句，你的进程没有包含。

tmpb<=x0 when cnt=0 else

x1 when cnt=1 else

x2 when cnt=2 else

y0 when cnt=3 else

y1 when cnt=4 else (others=>'0')

这里有问题吧

tmpb:std_logic_vector(4 downto 0)

y0,y1:in std_logic_vector(8 downto 0)

tmpb和y0、y1信号的位数不一样

entity cntb is

port(clk: in bit

q: buffer integer range 31 downto 0)

end cntb

architecture bhv of cntb is

begin

process(clk)

begin

if clk'event and clk='1' then

q <= q+1

end if

end process

end bhv

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