input a,b,c,d
input clk,res
output led1,led2,led3,led4
reg led1,led2,led3,led4
reg k
always @(clk)
begin
if(res==0)
begin
led1<=0
led2<=0
led3<=0
led4<=0
k<=0
end
else
begin
if(k==0)
begin
if(a)
begin
led1<=1
k<=1
end
else
if(b)
begin
led2<=1
k<=1
end
else
if(c)
begin
led3<=1
k<=1
end
if(d)
begin
led4<=1
k<=1
end
end
end
end
endmodule
/**********************************
（1）实现一四人抢答器，有人抢答成功后，其他人再抢答无效；
（2）通过蜂鸣器响1秒来提示抢答成功，并在数码管上显示抢答者的序号；
（3）主持人通过按键清除抢答信息，并开始 30 秒的答题倒计时，当倒计时
结束时，通过蜂鸣器响 1 秒来提示回答问题时间到，此时可以开始新一轮的抢答
************************************/
module qiangda(rst,clk,ina,inb,inc,ind,judge,clk_1hz,wei,duan,beep,wei1,duan1,clk_1khz)
input clk,clk_1hz
input ina,inb,inc,ind,judge
output[3:0] wei
output[7:0] duan
input rst,clk_1khz
output [3:0] wei1
output [7:0] duan1
output beep
reg[3:0] wei
reg[7:0] duan
reg flag
reg [5:0] shi,ge,data
reg [4:0] count
reg [3:0] wei1
reg [7:0] duan1
reg beep
reg yu
reg [1:0] count3
always @(posedge clk)
begin
if(!rst) //系统复位，个人认为复位不够完整
begin
yu = 0
end
if(!judge) //主持人控制按键
begin
flag=0 //允许抢答
wei=4'b1111 //数码管全不亮
//【个人认为分成duan1和duan，wei1和wei的数码管数据总线不经济】
duan=8'hff
yu=1 //重新开始倒计时
end
else
begin
if(ge==6'b000000&&shi==6'b000000) //处于等待状态，实际上是等主持人按键（!judge），
else
begin
if(!ina) //若a抢答
begin
if(!flag) //若无人抢答成功
begin
wei=4'b1101
duan=8'hf9 //数码管显示1，代表a抢答成功
flag=1 //抢答标志位有效
end
end
else if(!inb) //b抢答处理电路
begin
if(!flag)
begin
wei=4'b1101
duan=8'ha4 //数码管显示2,代表b抢答成功
flag=1
end
end
else if(!inc)
begin
if(!flag)
begin
wei=4'b1101
duan=8'hb0 //数码管显示3
flag=1
end
end
else if(!ind)
begin
if(!flag)
begin
wei=4'b1101
duan=8'h99 //数码管显示4
flag=1
end
end
end
end
end
always@(posedge clk_1hz or negedge rst)
begin
if(!rst)
begin
count = 0
end
else if(count >= 5'd30) //计时达到30秒，停止计时
count = count
else if(yu==1) //触发条件yu=1时，重新开始计数【那不是变成从30开始数？感觉该段有些问题】
count = count+5'b1
end
//以下always过程块为shi和ge的译码电路,完成倒计时功能
always @(count)
begin
if(count>=5'b10101) //count>20时
begin
shi = 5'b00000 //shi=0
ge = 5'b11110-count //ge = 30-count
end
else if(count>=5'b01011) //10<count<=20时
begin
shi=5'b00001 //shi=1
ge=5'b10100-count //ge = 20-count
end
else if(count>=5'b00001) //0<count<=10时
begin
shi=5'b00010 //shi=2
ge=5'b01010-count //ge = 10-count
end
else //其它情况,i.e. count = 0
begin
shi=5'b00011 //shi=3
ge=5'b0 //ge = 0
end
end
//以下always过程块为蜂鸣器发声驱动电路
always@(posedge clk_1hz)
if(flag|(shi==0&&ge==0)) //flag==1，有人抢答成功
//shi==0&&ge==0，倒计时结束
begin //上述两种情况下蜂鸣器响一秒
if(count3==2'b1)
begin
beep<=0
count3<=count3
end
else
begin
beep<=1
count3<=count3+2'b1
end
end
else
begin
beep<=0
count3<=0
end
//以下always过程块是数码管动态刷新电路，动态显示倒计时信息(shi和ge)
always @(clk_1khz)
begin
if(!rst)
wei1 = 4'b0000
else if(clk_1khz)
begin
wei1=4'b0111
data=ge
end
else
begin
wei1=4'b1011
data=shi
end
end
always @(data) //数字显示译码，共阳极数码管(duan1)
begin
case(data)
6'b000000: duan1=8'b1100_0000
6'b000001: duan1=8'b1111_1001
6'b000010: duan1=8'b1010_0100
6'b000011: duan1=8'b1011_0000
6'b000100: duan1=8'b1001_1001
6'b000101: duan1=8'b1001_0010
6'b000110: duan1=8'b1000_0010
6'b000111: duan1=8'b1111_1000
6'b001000: duan1=8'b1000_0000
6'b001001: duan1=8'b1001_0000
default:duan1=8'b1111_1111
endcase
end
endmodule
各模块VHDL源代码1、抢答鉴别模块FENG的VHDL源程序
--feng.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY FENG IS
PORT(CP,CLR:IN STD_LOGIC
Q :OUT STD_LOGIC)
END FENG
ARCHITECTURE FENG_ARC OF FENG IS
BEGIN
PROCESS(CP,CLR)
BEGIN
IF CLR='0'THEN
Q<='0'
ELSIF CP'EVENT AND CP='0'THEN
Q<='1'
END IF
END PROCESS
END FENG_ARC
2、片选信号产生模块SEL的VHDL源程序
--sel.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY SEL IS
PORT(CLK:IN STD_LOGIC
a:OUT INTEGER RANGE 0 TO 7)
END SEL
ARCHITECTURE SEL_ARC OF SEL IS 片选信号产生模块SEL
BEGIN
PROCESS(CLK)
VARIABLE AA:INTEGER RANGE 0 TO 7
BEGIN
IF CLK'EVENT AND CLK='1'THEN
AA:=AA+1
END IF
A<=AA
END PROCESS
END SEL_ARC
3、锁存器模块LOCKB的VHDL源程序
-lockb.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY LOCKB IS
PORT(D1,D2,D3,D4:IN STD_LOGIC
CLK,CLR:IN STD_LOGIC
Q1,Q2,Q3,Q4,ALM:OUT STD_LOGIC)
END LOCKB
ARCHITECTURE LOCK_ARC OF LOCKB IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLR='0'THEN
Q1<='0'
Q2<='0'
Q3<='0'
Q4<='0'
ALM<='0' 模块LOCKB
ELSIF CLK'EVENT AND CLK='1'THEN
Q1<=D1
Q2<=D2
Q3<=D3
Q4<=D4
ALM<='1'
END IF
END PROCESS
END LOCK_ARC
4、转换模块CH41A的VHDL源程序
--ch41a..vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY CH41A IS
PORT(D1,D2,D3,D4:IN STD_LOGIC
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
END CH41A
ARCHITECTURE CH41_ARC OF CH41A IS 转换模块CH41A
BEGIN
PROCESS(D1,D2,D3,D4)
VARIABLE TMP:STD_LOGIC_VECTOR(3 DOWNTO 0)
BEGIN
TMP:=D1&D2&D3&D4
CASE TMP IS
WHEN "0111"=>Q<="0001"
WHEN "1011"=>Q<="0010"
WHEN "1101"=>Q<="0011"
WHEN "1110"=>Q<="0100"
WHEN OTHERS=>Q<="1111"
END CASE
END PROCESS
END CH41_ARC
5、3选1模块CH31A的VHDL源程序
--ch31a.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY CH31A IS
PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
D1,D2,D3:IN STD_LOGIC_VECTOR(3 DOWNTO 0)
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
END CH31A
ARCHITECTURE CH31_ARC OF CH31A IS
BEGIN
PROCESS(SEL,D1,D2,D3)
BEGIN
CASE SEL IS
WHEN "000"=>Q<=D1
WHEN "001"=>Q<=D2
WHEN "111"=>Q<=D3
WHEN OTHERS=>Q<="1111"
END CASE
END PROCESS
END CH31_ARC
6、倒计时模块COUNT的VHDL源程序
倒计时模块COUNT如图16-7所示，该模块实现答题时间的倒计时，在计满100s后送出声音提示。
--count.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY COUNT IS
PORT(CLK,EN:IN STD_LOGIC倒计时 模块COUNT
H,L:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
SOUND:OUT STD_LOGIC)
END COUNT
ARCHITECTURE COUNT_ARC OF COUNT IS
BEGIN
PROCESS(CLK,EN)
VARIABLE HH,LL:STD_LOGIC_VECTOR(3 DOWNTO 0)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF EN='1'THEN
IF LL=0 AND HH=0 THEN
SOUND<='1'
ELSIF LL=0 THEN
LL:="1001"
HH:=HH-1
ELSE
LL:=LL-1
END IF
ELSE
SOUND<='0'
HH:="1001"
LL:="1001"
END IF
END IF
H<=HH
L<=LL
END PROCESS
END COUNT_ARC
7、显示译码模块DISP的VHDL源程序
--disp.vhd
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY DISP IS 显示译码模块DISP
PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0)
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0))
END DISP
ARCHITECTURE DISP_ARC OF DISP IS
BEGIN
PROCESS(D)
BEGIN
CASE D IS
WHEN"0000"=>Q<="0111111"
WHEN"0001"=>Q<="0000110"
WHEN"0010"=>Q<="1011011"
WHEN"0011"=>Q<="1001111"
WHEN"0100"=>Q<="1100110"
WHEN"0101"=>Q<="1101101"
WHEN"0110"=>Q<="1111101"
WHEN"0111"=>Q<="0100111"
WHEN"1000"=>Q<="1111111"
WHEN"1001"=>Q<="1101111"
WHEN OTHERS=>Q<="0000000"
END CASE
END PROCESS
END DISP_ARC
欢迎分享，转载请注明来源：内存溢出
微信扫一扫
支付宝扫一扫
评论列表（0条）