
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
entity ymq is
port
(
num:in std_logic_vector(3 downto 0)
dout:out std_logic_vector(6 downto 0)
)
end ymq
architecture a1 of ymq is
begin
with num select
dout<="1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"0000000" when others
end a1
如图所示,当X0为ON时,先给D0一个初始值9,然后利用T0循环计时,将D0自减一,使D0从9变化到0。同时利用七段译码指令SEGD,将D0的值进行译码,并输出到输出端子Y0到Y7中,当Y0到Y6分别接到数码管的a到g,数码管就显示9到0了。
望采纳。。。。。。。
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