半导体产业，设计和制造哪个难度大

制造难度大。

1、现在兼顾设计和制造的公司比较少；

2、只做设计公司很多，一般成为fabless，拥有电脑、软件和设计工程师就可以完成设计，输出设计后交由光罩厂、晶圆流片代工厂、封测厂生产器件。

3、只做制造的成为fab厂，门坎较高，一条8英寸晶圆流片生产线总投资可达10亿美元；且制造对工艺水平、化学用品管控、洁净程度要求很高。

4、关于设计和制造的盈利，设计公司出了一版设计，花一大笔钱去流片，器件卖得好才能盈利，否则一次流片就能让一个设计公司倒闭；fab厂只要有订单，设备在运转，就保证不亏本。

半导体制造简介：半导体的制造是一个复杂且耗时的过程。 首先要利用设计自动化软件开始电路设计，然后将集成电路设计的版图转印到石英玻璃上的铬膜层形成光刻板或倍缩光刻板；另一方面，由石英砂提炼出的初级硅经过纯化后拉成单晶硅棒，然后切片做成晶圆。晶圆经过边缘化和表面处理，再与光刻板/倍缩光刻板一起送到半导体制造厂制造集成电路芯片。半导体封装简介:半导体生产流程由晶圆制造、晶圆测试、芯片封装和封装后测试组成。半导体封装是指将通过测试的晶圆按照产品型号及功能需求加工得到独立芯片的过程。封装过程为：来自晶圆前道工艺的晶圆通过划片工艺后，被切割为小的晶片（Die），然后将切割好的晶片用胶水贴装到相应的基板（引线框架）架的小岛上，再利用超细的金属（金、锡、铜、铝）导线或者导电性树脂将晶片的接合焊盘（Bond Pad）连接到基板的相应引脚（Lead）,并构成所要求的电路；然后再对独立的晶片用塑料外壳加以封装保护，塑封之后，还要进行一系列 *** 作，如后固化（Post Mold Cure）、切筋和成型（Trim&Form）、电镀（Plating）以及打印等工艺。封装完成后进行成品测试，通常经过入检（Incoming）、测试（Test）和包装（Packing）等工序，最后入库出货。典型的封装工艺流程为：划片 装片 键合 塑封 去飞边 电镀 打印 切筋和成型 外观检查 成品测试 包装出货。

RF CMOS / SiGe HBT / GaAs HBT　

In the last years RF CMOS power amplifiers have been introduced. SiGe Bipolar power amplifiers are available since a couple of year already. But they have not established in volume supply in the hand-set industry as already mentioned. TriQuint also has been engaged in this technology over several years with the development and release of CDMA power amplifier, in SiGe and GaAs. This development team now is exclusively working on GaAs HBT based devices. The main reasons are performance cost. The long lasting dispute between Silicon and GaAs with arguments like: Silicon is more mature and predictable, can be produced at lower cost, and integrating new functions on chip is easier than in GaAs. In detail these are no longer true for today's challenging applications. GaAs processes have matured and cost disadvantages have been overcome by reaching volumes that have driven down substrate prices tremedously. Additionally GaAs has performance features that cannot always be metched by Silicon chip. Larger chip sizes have severe disadvantages because the die gets more expensive and secondly and even more important it has cost impact on the module and hampers the shrinkage path for future products. Chip cost for a SiGe chip with comparable performance and function are higher compared to a GaAs HBT die although the wafer cost still is lower, but the required die size is larger. SiGe RF power performance under high linearity requirements in high band for CDMA is not competitive to GaAs HBT. In a CDMA high band example the SiGe die was 2.5x the sizes of a GaAs solution resulted in a 15% lower cost for the full module.

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